DocumentCode
1292398
Title
Feedback in silicon compilers
Author
Friedman, Eby G.
Author_Institution
Hughes Aircraft Co., Carlsbad, CA, USA
Volume
1
Issue
3
fYear
1985
fDate
5/1/1985 12:00:00 AM
Firstpage
15
Lastpage
20
Abstract
In order for silicon compilers to become a truly viable VLSI design option, application-specific information must be extracted and used as feedback to permit optimization of chip designs. The author describes three significant phases necessary to provide feedback in silicon compilers and techniques for their implementation. To demonstrate the techniques and utility of providing feedback in silicon compilers, an example of feedback that uses layout-extracted interconnect impedances to parameterize buffer cells is described.
Keywords
VLSI; cellular arrays; circuit layout CAD; feedback; logic CAD; VLSI design; application-specific information; buffer cells; chip designs; circuit layout CAD; feedback; layout-extracted interconnect impedances; logic CAD; optimization; silicon compilers; Chip scale packaging; Data mining; Geometry; Integrated circuit interconnections; Layout; Silicon compiler; Very large scale integration;
fLanguage
English
Journal_Title
Circuits and Devices Magazine, IEEE
Publisher
ieee
ISSN
8755-3996
Type
jour
DOI
10.1109/MCD.1985.6311966
Filename
6311966
Link To Document