Efficient algorithmic decomposition of transistor groups into series, bridge, and parallel combinations

A novel approach to automatically decompose MOS transistor groups into pull-up, pull-down, and pass-transistor subgroups is described. The subgroups are further recursively decomposed into series, parallel, and bridge combinations, all in linear time. This approach is more powerful and efficient than existing ones and has important applications in static timing analysis, electrical verification, and simulation of MOS VLSI digital circuits. It has been implemented and tested in the timing analysis program TAMIA and requires as little as 0.0025 s/transistor to decompose a large circuit on a SUN3 computer