Title :
CMOS switched-op-amp-based sample-and-hold circuit
Author :
Dai, Liang ; Harjani, Ramesh
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
This paper presents a sample-and-hold design that is based on a switched-op-amp topology. Charge injection errors are greatly reduced by turning off transistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feed through error is mostly signal-independent and is cancelled out by a pseudodifferential topology. Switched-opamps are designed and fabricated in a 2-/spl mu/ CMOS technology. The measurement results show that the harmonics are at least 78 dB below the signal level. Both the measurement results from fabricated ICs and simulation results suggest the potential benefits of this approach in comparison to traditional switched-capacitor circuits.
Keywords :
CMOS analogue integrated circuits; operational amplifiers; sample and hold circuits; switched networks; 2 micron; CMOS switched-opamp sample-and-hold circuit; charge injection error; clock feed through error; pseudo-differential topology; CMOS technology; Circuit simulation; Circuit topology; Clocks; Feeds; MOSFETs; Switched capacitor circuits; Switches; Switching circuits; Turning;
Journal_Title :
Solid-State Circuits, IEEE Journal of
