Title :
The block distributed memory model
Author :
JáJá, Joseph F. ; Ryu, Kwan Woo
Author_Institution :
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
fDate :
8/1/1996 12:00:00 AM
Abstract :
We introduce a computation model for developing and analyzing parallel algorithms on distributed memory machines. The model allows the design of algorithms using a single address space and does not assume any particular interconnection topology. We capture performance by incorporating a cost measure for interprocessor communication induced by remote memory accesses. The cost measure includes parameters reflecting memory latency, communication bandwidth, and spatial locality. Our model allows the initial placement of the input data and pipelined prefetching. We use our model to develop parallel algorithms for various data rearrangement problems, load balancing, sorting, FFT, and matrix multiplication. We show that most of these algorithms achieve optimal or near optimal communication complexity while simultaneously guaranteeing an optimal speed-up in computational complexity. Ongoing experimental work in testing and evaluating these algorithms has thus far shown very promising results
Keywords :
communication complexity; computational complexity; distributed memory systems; fast Fourier transforms; matrix multiplication; parallel algorithms; performance evaluation; resource allocation; sorting; FFT; block distributed memory model; communication bandwidth; communication complexity; computation model; computational complexity; cost measure; data rearrangement problems; distributed memory machines; interconnection topology; interprocessor communication; load balancing; matrix multiplication; memory latency; parallel algorithms; performance; remote memory accesses; single address space; sorting; spatial locality; Algorithm design and analysis; Bandwidth; Computational modeling; Concurrent computing; Costs; Delay; Distributed computing; Parallel algorithms; Prefetching; Topology;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on