Title :
ESD protection for deep submicron triple well CMOS technologies
Author :
Nikolaidis, T. ; Papadas, C.
Author_Institution :
ISD S.A., Athens, Greece
fDate :
11/11/1999 12:00:00 AM
Abstract :
The turn-on mechanism of an ESD protection NMOS transistor constructed with deep submicron triple well CMOS technology is studied. Owing to P-well coupling, this transistor exhibits a reduced trigger voltage level. An efficient ESD protection circuit for overall ESD reliability of an integrated circuit is also proposed
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; protection; ESD protection; NMOS transistor; P-well coupling; deep submicron triple well CMOS technology; integrated circuit; reliability; trigger voltage; turn-on mechanism;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991393
