• DocumentCode
    129357
  • Title

    Magnetic memories: From DRAM replacement to ultra low power logic chips

  • Author

    Prenat, G. ; Di Pendina, G. ; Layer, C. ; Goncalves, O. ; Jaber, Khaled ; Dieny, Bernard ; Sousa, Ricardo ; Prejbeanu, Ioan L. ; Nozieres, J.P.

  • Author_Institution
    Spintec, 17, Rue des Martyrs, 38054 Grenoble Cedex, France
  • fYear
    2014
  • fDate
    24-28 March 2014
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    The recent advent of spin transfer torque (STT) has shed a new light on MRAM with the promises of much improved performances and greater scalability to very advanced technology nodes. As a result, MRAM is now viewed as a credible solution for stand-alone and embedded applications where the combination of non-volatility, speed and endurance is key. Whereas the technology is nearing maturity for DRAM replacement, with the exception of process scaling to sub-20nm which remains a challenge, circuit designers are now actively looking at SoCs where MRAM could bring in better performance and lower power consumption in data intensive applications as well as instant-on capability in mobile applications. In this paper we present a review of the MRAM technology and a methodology for ASIC design using a custom full digital hybrid CMOS/Magnetic Process Design Kit. We finish by a few examples showing that magnetic memories can be efficiently integrated in logic designs, for both safety and low power purposes.
  • Keywords
    MRAM; hybrid CMOS; spin transfer torque;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
  • Conference_Location
    Dresden
  • Type

    conf

  • DOI
    10.7873/DATE.2014.281
  • Filename
    6800482