An efficient memory system for the SIMD construction of a Gaussian pyramid

In this paper, a memory system is introduced for the efficient construction of a Gaussian pyramid. The memory system consists of an address calculating circuit, an address routing circuit, a memory module selection circuit, and 2ⁿ+1 memory modules. The memory system provides parallel access to 2ⁿ image points whose patterns are a block, a row or a column, where the interval of the column and the block is 1 and the interval of the row is 2^l,l⩾0. The performance of a generic SIMD (single-instruction multiple-data) processor using the proposed memory system is compared with one using an interleaved memory system for the construction of a Gaussian pyramid. The ratio of the time of the construction of level 2 and level 10 from the original image (level 0) of an SIMD processor with an interleaved memory system to that of the proposed memory system is 1.485 and 1.633, respectively