Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations

Author

Roche, Ph. ; Palau, J.-M. ; Bruguier, G. ; Tavernier, C. ; Ecoffet, R. ; Gasiot, J.

Author_Institution

CEM2, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

Volume

46

Issue

6

fYear

1999

Firstpage

1354

Lastpage

1362

Abstract

A 3-D entire SRAM cell, based on a 0.35-/spl mu/m current CMOS technology, is simulated in this work with a DEVICE simulator. The transient current, resulting from a heavy ion strike in the most sensitive region of the cell, is studied as a function of the LET value, the cell layout and the ion penetration depth. A definition of the critical charge is proposed and two new methods are presented to compute this basic amount of charge only using SPICE simulations. Numerical applications are performed with two different generations of submicron CMOS technologies, including the determination of the sensitive thicknesses.

Keywords

CMOS memory circuits; SPICE; SRAM chips; cellular arrays; circuit simulation; ion beam effects; 0.35 micron; 3D full cell SRAM simulations; CMOS technology; DEVICE simulator; LET value; SEU occurrence; SPICE simulations; cell layout; heavy ion strike; ion penetration depth; sensitive thicknesses; transient current; CMOS process; CMOS technology; Circuit simulation; Computational modeling; Predictive models; Process design; Random access memory; SPICE; Semiconductor device modeling; Semiconductor process modeling;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.819093

Filename

819093