Cell design modifications to harden an N-channel power IGBT against single event latchup

Author

Lorfevre, E. ; Sagnes, B. ; Bruguier, G. ; Palau, J.M. ; Gasiot, J. ; Calvet, M.C. ; Ecoffet, R.

Author_Institution

CEM2, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

Volume

46

Issue

6

fYear

1999

Firstpage

1410

Lastpage

1414

Abstract

A device simulator is used to analyze the heavy ion induced failure mechanism in insulated gate bipolar transistors (IGBTs) and to investigate hardening solutions. Single event latchup was already identified as the failure mechanism. Lateral and vertical modifications of the P/sup +/ plug are proposed to reduce the efficiency of the parasitic thyristor, responsible for the latchup, and validated by 2D-simulations on a N-channel IGBT cell structure.

Keywords

failure analysis; insulated gate bipolar transistors; ion beam effects; power transistors; radiation hardening (electronics); semiconductor device models; semiconductor device reliability; thyristors; 2D-simulations; N-channel power IGBT; cell design modifications; heavy ion induced failure mechanism; lateral modifications; parasitic thyristor; single event latchup; vertical modifications; Analytical models; Failure analysis; Impedance; Insulated gate bipolar transistors; MOSFET circuits; Plugs; Power MOSFET; Semiconductor process modeling; Space technology; Thyristors;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.819100

Filename

819100