Title :
SEU testing of a novel hardened register implemented using standard CMOS technology
Author :
Monnier, T. ; Roche, F.M. ; Cosculluela, J. ; Velazco, R.
Author_Institution :
Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Abstract :
A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron non-radiation hardened CMOS technology. This paper presents the results of heavy ion tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact on the real estate, write time, or power consumption.
Keywords :
CMOS digital integrated circuits; integrated circuit reliability; integrated circuit testing; ion beam effects; radiation hardening (electronics); shift registers; LET threshold; SEU testing; SEU-robustness; cross-section; hardened register; heavy ion tests; memory structure; power consumption; standard CMOS technology; CMOS technology; Circuits; DH-HEMTs; Filtering; Impedance; Latches; Radiation hardening; Registers; Robots; Testing;
Journal_Title :
Nuclear Science, IEEE Transactions on
