Title :
Overcoming scaling concerns in a radiation-hardened CMOS technology
Author :
Maimon, J. ; Hadda, N.
Author_Institution :
Lockheed Martin Space Electron. & Commun., Manassas, VA, USA
Abstract :
Scaling efforts to develop an advanced radiation-hardened CMOS process to support a 4M SRAM are described. Issues encountered during scaling of transistor, isolation, and resistor elements are discussed, as well as the solutions used to overcome these issues. Transistor data, total dose radiation results, and the performance of novel resistors for prevention of single event upsets (SEU) are presented.
Keywords :
CMOS integrated circuits; SRAM chips; integrated circuit design; integrated circuit reliability; integrated circuit testing; isolation technology; radiation hardening (electronics); 4 Mbit; SRAM; isolation; radiation-hardened CMOS technology; resistor elements; scaling; single event upsets; total dose radiation; transistor; transistor data; CMOS process; CMOS technology; Etching; Isolation technology; Random access memory; Resistors; Silicon; Single event upset; Space technology; Transistors;
Journal_Title :
Nuclear Science, IEEE Transactions on
