Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

Author

Anelli, G. ; Campbell, M. ; Delmastro, M. ; Faccio, F. ; Floria, S. ; Giraldo, A. ; Heijne, E. ; Jarron, P. ; Kloukinas, K. ; Marchioro, A. ; Moreira, P. ; Snoeys, W.

Author_Institution

CERN, Geneva, Switzerland

Volume

46

Issue

6

fYear

1999

Firstpage

1690

Lastpage

1696

Abstract

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT´s) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC´s designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT´s: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC´s conceived with this design approach are finally drawn.

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; integrated circuit testing; radiation hardening (electronics); 100 Mrad; ASICs; LHC experiment; Large Hadron Collider; W/L ratio; density; design aspects; enclosed layout transistors; guard rings; matching properties; noise; radiation tolerance; radiation tolerant VLSI circuits; speed; standard deep submicron CMOS technologies; CMOS technology; Circuits; Large Hadron Collider; Leakage current; Noise measurement; Semiconductor device modeling; Signal to noise ratio; Testing; Transistors; Very large scale integration;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.819140

Filename

819140