Enhanced total ionizing dose tolerance of bulk CMOS transistors fabricated for ultra-low power applications

The first radiation tests of transistors fabricated in a commercial bulk CMOS process designed for ultra-low power applications in space are presented and analyzed. The predominant failure mode of bulk CMOS, i.e., radiation-induced parasitic leakage currents in n-channel transistors, is greatly suppressed by the use of low threshold voltage devices and by the application of backbias used to optimize their performance. With 2 volts of backbias applied, the transistors tested here show no degradation up to a dose of 200 krad(Si).