Title :
Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage
Author :
Ebrahimi, Behzad ; Rostami, Masoud ; Afzali-Kusha, Ali ; Pedram, Massoud
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
Abstract :
In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.
Keywords :
MOSFET; SRAM chips; circuit optimisation; particle swarm optimisation; statistical distributions; FinFET SRAM; FinFET design; SRAM array; SRAM cell; back-gate voltage; gate length; optimization knob; particle swarm optimization; silicon thickness; statistical correlation; statistical design optimization; statistical distribution; time failure; Design optimization; Failure analysis; FinFETs; Optimization methods; Random access memory; Silicon; Stability; Statistical distributions; Switches; Threshold voltage; Back-gate design; FinFET; SRAM; design for manufacturability; process variations; yield;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2059054
