A scaleable, radiation hardened shallow trench isolation

Author

Brady, F.T. ; Maimon, J.D. ; Hurt, M.J.

Author_Institution

Lockheed Martin Space Electron. & Commun., Manassas, VA, USA

Volume

46

Issue

6

fYear

1999

Firstpage

1836

Lastpage

1840

Abstract

Shallow trench isolation (STI) is rapidly replacing LOCOS (LOCal Oxidation of Silicon) as the device isolation process of choice. However, little work has been done to characterize the radiation-hardness capability of devices built with STI. In this paper, some of the basics of STI devices are examined, such as the radiation response of unhardened STI devices. We discuss several issues affecting the total dose hardness of unhardened STI. These issues have critical implications for the hardness of CMOS built using STI in commercial foundries. Finally, data from hardened STI devices are presented. Total dose hardened STI devices are demonstrated on devices with gate widths down to 0.5 /spl mu/m.

Keywords

CMOS integrated circuits; integrated circuit reliability; isolation technology; leakage currents; radiation hardening (electronics); silicon-on-insulator; 0.5 micron; CMOS; STI; device isolation process; gate widths; radiation hardened shallow trench isolation; radiation response; radiation-hardness capability; total dose hardness; CMOS technology; Contracts; Etching; Foundries; Oxidation; Radiation hardening; Scalability; Silicon; Temperature; Threshold voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.819162

Filename

819162