• DocumentCode
    1294439
  • Title

    Anti-Imaging Time-Mode Filter Design Using a PLL Structure With Transfer Function DFT

  • Author

    Aouini, Sadok ; Chuai, Kun ; Roberts, Gordon W.

  • Author_Institution
    Integrated Microsyst. Lab., McGill Univ., Montreal, QC, Canada
  • Volume
    59
  • Issue
    1
  • fYear
    2012
  • Firstpage
    66
  • Lastpage
    79
  • Abstract
    This paper presents a pole-zero placement approach for designing arbitrary-order time-mode filters for anti-imaging (reconstruction) applications. One application is for phase-domain sigma-delta modulation involving digital-to-time converters. The time-mode filters are constructed from an th-order type-II PLL single-loop feedback structure involving an active loop filter of order . The tradeoffs in terms of PLL order, noise bandwidth, settling- and lock-time, and the impact of the voltage-controlled oscillator (VCO) phase noise on the performance of the time-mode filter are investigated. A sixth-order PLL is designed and fabricated on a printed circuit board and is used to validate the proposed synthesis method. In addition, an all-digital phase stimulus generation method well suited to a digital scan-based design-for-test (DFT) approach for testing the frequency response behavior of time-mode filters and other PLL-based designs is proposed.
  • Keywords
    active filters; circuit feedback; design for testability; frequency response; phase locked loops; phase noise; printed circuits; sigma-delta modulation; transfer functions; voltage-controlled oscillators; DFT transfer function; PLL structure; VCO phase noise; active loop filter; all-digital phase stimulus generation method; antiimaging time-mode filter design; arbitrary-order time-mode filter design; digital scan-based design-for-test approach; digital-to-time converters; frequency response behavior; noise bandwidth; phase-domain sigma-delta modulation; pole-zero placement approach; printed circuit board; th-order type-II PLL single-loop feedback structure; voltage-controlled oscillator; Encoding; Phase locked loops; Poles and zeros; Polynomials; Sigma delta modulation; Voltage-controlled oscillators; Analog circuits; design for testability (DFT); phase-locked loops (PLLs); sigma-delta modulation; time-mode filters;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2011.2161411
  • Filename
    5979213