Title :
Memory-constrained static rate-optimal scheduling of synchronous dataflow graphs via retiming
Author :
Xue-Yang Zhu ; Geilen, M. ; Basten, Twan ; Stuijk, Sander
Author_Institution :
State Key Lab. of Comput. Sci., Inst. of Software, Beijing, China
Abstract :
Synchronous dataflow graphs (SDFGs) are widely used to model digital signal processing (DSP) and streaming media applications. In this paper, we use retiming to optimize SDFGs to achieve a high throughput with low storage requirement. Using a memory constraint as an additional enabling condition, we define a memory constrained self-timed execution of an SDFG. Exploring the state-space generated by the execution, we can check whether a retiming exists that leads to a rate-optimal schedule under the memory constraint. Combining this with a binary search strategy, we present a heuristic method to find a proper retiming and a static scheduling which schedules the retimed SDFG with optimal rate (i.e., maximal throughput) and with as little storage space as possible. Our experiments are carried out on hundreds of synthetic SDFGs and several models of real applications. Differential synthetic graph results and real application results show that, in 79% of the tested models, our method leads to a retimed SDFG whose rate-optimal schedule requires less storage space than the proven minimal storage requirement of the original graph, and in 20% of the cases, the returned storage requirements equal the minimal ones. The average improvement is about 7.3%. The results also show that our method is computationally efficient.
Keywords :
data flow graphs; directed graphs; heuristic programming; scheduling; search problems; DSP; SDFGs; binary search strategy; differential synthetic graph; digital signal processing; heuristic method; media streaming; memory constrained self-timed execution; memory-constrained static rate-optimal scheduling; static scheduling; storage space; synchronous dataflow graphs via retiming; Computational modeling; Delays; Digital signal processing; Memory management; Schedules; Throughput; Vectors;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
DOI :
10.7873/DATE.2014.338