Reduction in energy consumption by bootstrapped n MOS switches in reversible adiabatic CMOS circuits

For ultra-low-energy applications, bootstrapped reversible-energy-recovery logic (bRERL) is proposed, which is a reversible adiabatic CMOS logic and requires an 8-phase clock. In bRERL, each transmission gate was replaced by a bootstrapped n MOS switch in the logic functional blocks of tRERL. Using SPICE simulations, it was confirmed that the bRERL circuit consumed less energy and occupied less area than the tRERL circuit. The authors integrated a bRERL inverter chain with its 8-phase, clocked power generator in a test chip, which was fabricated with 0.6 μm CMOS technology. They also confirmed that they could minimise the energy consumption in the bRERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal