• DocumentCode
    1295420
  • Title

    On buried oxide effects in SOI lateral bipolar transistors

  • Author

    Banna, Srinivasa R. ; Chan, Philip C.H. ; Lau, Jack

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong
  • Volume
    44
  • Issue
    1
  • fYear
    1997
  • fDate
    1/1/1997 12:00:00 AM
  • Firstpage
    139
  • Lastpage
    144
  • Abstract
    We report buried oxide effects on the Silicon-On-Insulator Lateral Bipolar Transistor (SOILBT) performance by two-dimensional (2-D) numerical simulation and experiments. An early punchthrough is observed in SOILBT compared to the bulk due to the presence of buried oxide. In addition to dopant segregation into the buried oxide, the presence of buried oxide also diverts some electric field lines emanating from collector toward substrate, due to 2-D distribution of field, leaving fewer across the base region and hence increased depletion widths and punchthrough. One-dimensional (1-D) depletion approximation fails to predict this punchthrough. To establish the evidence of buried oxide induced punchthrough without dopant segregation effect, simple and yet novel measurement techniques are proposed to extract effective base width and base doping concentration near the buried oxide-silicon film interface using the parasitic MOSFET in SOILBT. Good agreement between 2-D simulation and experimental results was observed. Finally design curves are generated using 2-D numerical simulation for different base doping and buried oxide thicknesses on SOI substrates
  • Keywords
    bipolar transistors; buried layers; doping profiles; segregation; semiconductor device models; silicon-on-insulator; SOI lateral bipolar transistors; SOILBT; Si-SiO2; base doping concentration; buried oxide effects; buried oxide-Si film interface; depletion widths; design curves; dopant segregation; early punchthrough; effective base width; electric field lines; measurement techniques; minimum base width; parasitic MOSFET; two-dimensional numerical simulation; BiCMOS integrated circuits; Bipolar transistors; Doping; Fabrication; Isolation technology; Measurement techniques; Medical simulation; Numerical simulation; Silicon on insulator technology; Substrates;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.554803
  • Filename
    554803