Optimization of interconnection-induced breakdown voltage in junction isolated IC´s using biased polysilicon field plates

Author

Murray, Anthony F J ; Lane, William A.

Author_Institution

Inst. of Adv. Microelectron., Nat. Microelectron. Res. Centre, Cork, Ireland

Volume

44

Issue

1

fYear

1997

fDate

1/1/1997 12:00:00 AM

Firstpage

185

Lastpage

189

Abstract

The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-μm wide wire

Keywords

circuit optimisation; electric breakdown; integrated circuit interconnections; isolation technology; power integrated circuits; 50 micron; 700 V; HV interconnection; HVIC process; Si; biased polysilicon field plates; blocking capability; high-voltage integrated circuit; interconnection-induced breakdown voltage; junction isolated IC; Breakdown voltage; Diodes; Electric breakdown; Integrated circuit interconnections; LAN interconnection; Microelectronics; Numerical simulation; Resistors; Wire; Wiring;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.554809

Filename

554809