A Model of the Gate Capacitance of Surrounding Gate Transistors: Comparison With Double-Gate MOSFETs

Author

Ruiz, Francisco J Garcìa ; Tienda-Luna, Isabel Marìa ; Godoy, Andrés ; Donetti, Luca ; Gámiz, Francisco

Author_Institution

Dept. de Electron. y Tecnol. de los Comput., Univ. de Granada, Granada, Spain

Volume

57

Issue

10

fYear

2010

Firstpage

2477

Lastpage

2483

Abstract

In this work, we develop a comprehensive model of the total gate capacitance (C_G) of circular-cross-section surrounding gate transistors that accounts for both the insulator gate capacitance (C_ins) and the inversion capacitance (C_inv). The accuracy of the model is checked with the results obtained from the numerical simulation of the structure. Using this model, we compare the C_G/C_ins ratio with that of double-gate (DG) transistors and study the degradation of the total gate capacitance of both devices as a function of the gate voltage and device size. It is shown that the C_G/C_ins ratio is higher in DGs, particularly for very small devices.

Keywords

MOSFET; insulators; numerical analysis; semiconductor device models; circular-cross-section surrounding gate transistors; double-gate MOSFET; insulator gate capacitance; inversion capacitance; numerical simulation; total gate capacitance model; Capacitance; Character generation; Degradation; Electrostatics; Geometry; Insulation; Insulators; Logic gates; MOSFETs; Mathematical model; Numerical simulation; Quantum capacitance; Silicon; Silicon on insulator technology; Tin; Double gate (DG); gate capacitance; nanowires; quantum effects; semiconductor device modeling; silicon-on-insulator (SOI) technology; surrounding gate transistors (SGTs);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2010.2058630

Filename

5549881