• DocumentCode
    1296203
  • Title

    The TigerSHARC DSP architecture

  • Author

    Fridman, Jose ; Greenfield, Zvi

  • Author_Institution
    Analog Devices Inc., Norwood, MA, USA
  • Volume
    20
  • Issue
    1
  • fYear
    2000
  • Firstpage
    66
  • Lastpage
    76
  • Abstract
    This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 MFLOPS (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point)
  • Keywords
    digital signal processing chips; memory architecture; parallel architectures; 900 MFLOPS; DSP architecture; TigerSHARC; short-vector memory system; sustained performance; Computer architecture; Concurrent computing; Digital signal processing; Digital signal processing chips; Filtering algorithms; Finite impulse response filter; Floating-point arithmetic; IIR filters; Memory architecture; Signal processing algorithms;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.820055
  • Filename
    820055
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1296203