Concurrent error detection and fault location in a gracefully degrading ATM switch

The authors present a concurrent error detection and fault location technique for a gracefully degrading ATM switch. The switch architecture has multiple data and control planes, each of which has an identical banyan topology. Cell headers are routed via the control planes to reserve their routing paths on the data planes. Multiplicity of data planes for enhancing performance is utilised to detect errors and locate faults during normal operation. An efficient algorithm is developed to locate faulty links or switching elements while normal switching operation is being performed. Periodic checking, where the test interval is determined dynamically depending on the traffic load, is suggested to minimise the performance degradation. The identified faulty data planes can also be made usable for cell transmission