Compiler-directed cache management in multiprocessors

Author

Cheong, Hoichi ; Veidenbaum, Alexander V.

Author_Institution

Illinois Univ., Urbana, IL, USA

Volume

23

Issue

6

fYear

1990

fDate

6/1/1990 12:00:00 AM

Firstpage

39

Lastpage

47

Abstract

The necessity of finding alternatives to hardware-based cache coherence strategies for large-scale multiprocessor systems is discussed. Three different software-based strategies sharing the same goals and general approach are presented. They consist of a simple invalidation approach, a fast selective invalidation scheme, and a version control scheme. The strategies are suitable for shared-memory multiprocessor systems with interconnection networks and a large number of processors. Results of trace driven simulations conducted on numerical benchmark routines to compare the performance of the three schemes are presented.<>

Keywords

buffer storage; multiprocessing systems; storage management; compiler directed cache management; fast selective invalidation scheme; interconnection networks; invalidation approach; multiprocessors; numerical benchmark routines; shared-memory; software-based strategies; trace driven simulations; version control scheme; Large-scale systems; Multiprocessing systems; Multiprocessor interconnection networks; Numerical simulation;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.55499

Filename

55499