Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping

Author

Islam, Md Ashraful ; Wahid, Khan A.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Saskatchewan, Saskatoon, SK, Canada

Volume

57

Issue

9

fYear

2010

Firstpage

716

Lastpage

720

Abstract

In this brief, we present an efficient design of a shared architecture to compute two 8-point Daubechies wavelet transforms. The architecture is based on a two-level folded mapping technique that is developed on the factorization and decomposition of transform matrices exploiting the symmetrical structure. The chip occupies a 2.08-mm² silicon area, runs at 100 MHz, and consumes 4.51 mW of power in 0.18-m CMOS technology.

Keywords

CMOS integrated circuits; digital arithmetic; integrated circuit design; microprocessor chips; wavelet transforms; CMOS technology; Daubechies wavelet transforms; algebraic integer quantization; area-efficient design; folded AIQ mapping; frequency 100 MHz; power 4.51 mW; power-efficient design; size 0.18 mum; transform matrices; Computer architecture; Costs; Discrete transforms; Discrete wavelet transforms; Hardware; Image coding; Matrix decomposition; Quantization; Silicon; Throughput; Wavelet transforms; Algebraic integer quantization (AIQ); Daubechies wavelet; error-free algorithm; folded mapping;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2010.2056111

Filename

5549905