• DocumentCode
    1296675
  • Title

    Compromise Impedance Match Design for Pogo Pins With Different Single-Ended and Differential Signal-Ground Patterns

  • Author

    Sun, Ruey-Bo ; Wu, Ruey-Beei ; Hsiao, Shih-Wei ; De Zutter, Daniël

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    33
  • Issue
    4
  • fYear
    2010
  • Firstpage
    953
  • Lastpage
    960
  • Abstract
    A new concept of compromise impedance match design is proposed for pogo pins with various signal-ground patterns. To begin with, the methodologies of equivalent circuit modeling for single-ended and differential pogo pins are described. A de-embedding technique is proposed to eliminate the effect of a specialized test fixture for the characterization of the pogo pins. Good agreement is found from the comparison between measured and simulated results, which validates the modeling and simulation methodologies. Then, the reflection of pogo pins with various signal-ground patterns is investigated and the optimal pin radius to pitch ratio is found to be 0.20-0.21, thereby achieving a return loss better than 15 dB for all these patterns in both single-ended and differential configurations from dc to 10 GHz. In addition, the effects of pin length are considered and a general design chart is constructed for determining the pogo pin geometry and the applicable impedance range to meet the specification on the return loss. Several compromise impedance design applications demonstrating the proposed methods are given.
  • Keywords
    equivalent circuits; geometry; impedance matching; compromise impedance match design; differential signal-ground patterns; equivalent circuit modeling; pogo pin geometry; pogo pins; single-ended signal-ground patterns; Circuit simulation; Circuit testing; Equivalent circuits; Fixtures; Geometry; Impedance; Integrated circuit modeling; Pattern matching; Pins; Power transmission lines; Reflection; Signal design; Sockets; Transmission line measurements; Compromise impedance design; pin patterns; pogo pin; return loss; signal integrity;
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/TADVP.2010.2044794
  • Filename
    5549955