DocumentCode :
1296853
Title :
A Novel Programmable Parallel CRC Circuit
Author :
Grymel, Martin ; Furber, Steve B.
Author_Institution :
Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
Volume :
19
Issue :
10
fYear :
2011
Firstpage :
1898
Lastpage :
1902
Abstract :
A new hardware scheme for computing the transition and control matrix of a parallel cyclic redundancy checksum is proposed. This opens possibilities for parallel high-speed cyclic redundancy checksum circuits that reconfigure very rapidly to new polynomials. The area requirements are lower than those for a realization storing a precomputed matrix. An additional simplification arises as only the polynomial needs to be supplied. The derived equations allow the width of the data to be processed in parallel to be selected independently of the degree of the polynomial. The new design has been simulated and outperforms a recently proposed architecture significantly in speed, area, and energy efficiency.
Keywords :
cyclic redundancy check codes; flip-flops; parallel architectures; polynomial matrices; control matrix; energy efficiency; hardware scheme; parallel cyclic redundancy checksum; parallel high-speed cyclic redundancy checksum circuits; polynomial degree; polynomials; precomputed matrix; programmable parallel CRC circuit; Circuits; Concurrent computing; Cyclic redundancy check; Cyclic redundancy check codes; Energy efficiency; Equations; Hardware; Logic; Polynomials; Protection; Cyclic redundancy checksum (CRC); digital logic; error detection; parallel; programmable;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2010.2058872
Filename :
5549980
Link To Document :
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