• DocumentCode
    1297060
  • Title

    Fault Modeling and Worst-Case Test Vectors for Logic Failure Induced by Total-Dose in Combinational Circuits of Cell-Based ASICs

  • Author

    Abou-Auf, Ahmed A. ; Abdel-Aziz, Hamzah A. ; Abdel-Aziz, Mostafa M.

  • Author_Institution
    Electron. Eng. Dept., American Univ. in Cairo, New Cairo, Egypt
  • Volume
    57
  • Issue
    4
  • fYear
    2010
  • Firstpage
    1978
  • Lastpage
    1985
  • Abstract
    We developed a methodology for identifying worst-case test vectors for logic faults induced by total dose in combinational circuits of cell-based ASICs. This methodology is independent of the design tools and the process technology.
  • Keywords
    CMOS logic circuits; application specific integrated circuits; combinational circuits; fault diagnosis; integrated circuit modelling; logic design; CMOS process technology; cell-based ASIC; combinational circuits; design tools; fault modeling; logic failure; worst-case test vectors; Application specific integrated circuits; CMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Fault diagnosis; Inverters; Logic devices; Logic gates; Logic testing; MOSFETs; Sensitivity; Voltage; CMOS; logic faults; test vectors; total dose; worst-case;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2010.2050071
  • Filename
    5550296
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1297060