• DocumentCode
    1297150
  • Title

    Effect of emitter contact materials on high-performance vertical p-n-p transistors

  • Author

    Ratanaphanyarat, S. ; Rausch, W. ; Smadi, M. ; Saccamango, Mary Jo ; Mei, S.N. ; Chu, Shao-Fu ; Ronsheim, P.A. ; Chu, J.O.

  • Author_Institution
    IBM Gen. Technol. Div., Hopewell Junction, NY, USA
  • Volume
    12
  • Issue
    6
  • fYear
    1991
  • fDate
    6/1/1991 12:00:00 AM
  • Firstpage
    261
  • Lastpage
    263
  • Abstract
    Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements.<>
  • Keywords
    bipolar transistors; boron; elemental semiconductors; semiconductor doping; semiconductor epitaxial layers; semiconductor technology; silicon; DC current gain; LTE; breakdown voltages; current gain measurements; device characteristics; emitter contact material; emitter junction depth; emitter resistance; emitter-collector punchthrough voltage; epitaxial Si:B emitter; high-performance vertical p-n-p transistors; in situ doped low temperature epitaxial Si emitters; in situ doped polysilicon emitters; ion-implant doped polysilicon emitter devices; narrow-emitter effect; polycrystalline Si:B emitter; polysilicon emitter devices; semiconductors; shallow junction vertical p-n-p transistors; Boron; Circuits; Current measurement; Electrical resistance measurement; Electron emission; Fabrication; Gain measurement; P-n junctions; Silicon; Substrates;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.82054
  • Filename
    82054