Title :
Forward Computations for Context-Adaptive Variable-Length Coding Design
Author :
Hsia, Shih-Chang ; Liao, Wen-Hsien
Author_Institution :
Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Kaohsiung, Taiwan
Abstract :
This brief presents an innovative high-speed context-adaptive variable-length encoder. First, a direct forward algorithm rather than backward tracking is proposed to compute the coding parameters. The forward computation without data reordering can shorten the latency time and the processing cycle. Based on the algorithm, the real-time chip is designed with a parallel structure and pipelined control, which can encode one codeword per cycle. The maximum processing time for one block is the number of nonzero coefficients (NC)+4 cycles. The output bit rate can achieve 125 M/s when implemented with 0.18- μm CMOS technology. The chip occupies about 15 k gates, and the power dissipation is about 5.38 mW.
Keywords :
CMOS logic circuits; adaptive codes; entropy; variable length codes; video coding; CMOS technology; H.264-AVC codec; advanced video coding techniques; backward tracking; context-adaptive variable-length coding design; direct forward algorithm; entropy coding; forward computation; high-speed context-adaptive variable-length encoder; latency time; parallel structure; pipelined control; power 5.38 mW; processing cycle; real-time chip; Automatic voltage control; Circuits; Computer architecture; Concurrent computing; Delay; Encoding; Entropy coding; HDTV; Logic gates; Processor scheduling; Real time systems; Registers; Schedules; Video coding; Context-adaptive variable-length coding (CAVLC); H.264/advanced video coding (AVC); VLSI architecture; entropy coding;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2010.2050956
