• DocumentCode
    1298281
  • Title

    Parallel BIST architecture for CAMs

  • Author

    Kang, Yong-Seok ; Lee, Jong-Cheol ; Kang, Sungho

  • Author_Institution
    Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
  • Volume
    33
  • Issue
    1
  • fYear
    1997
  • fDate
    1/2/1997 12:00:00 AM
  • Firstpage
    30
  • Lastpage
    31
  • Abstract
    A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved
  • Keywords
    built-in self test; content-addressable storage; integrated circuit testing; parallel architectures; CAM; algorithm; built-in self test; content addressable memory; parallel BIST architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19970020
  • Filename
    555059
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1298281