Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs

Author

Suzuki, Eiichi ; Ishii, Kenichi ; Kanemaru, Seigo ; Maeda, Tatsuro ; Tsutsumi, Toshiyuki ; Sekigawa, Toshihiro ; Nagai, Kiyoko ; Hiroshima, Hiroshi

Author_Institution

Electrotech. Lab., Ibaraki, Japan

Volume

47

Issue

2

fYear

2000

fDate

2/1/2000 12:00:00 AM

Firstpage

354

Lastpage

359

Abstract

We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFET´s in the 40-135 nm gate length regime. It is experimentally and systematically found that the threshold voltage (V_th) roll-off and subthreshold slope (S-slope) are highly suppressed as the channel SOI thickness is reduced. The experimental 40-nm gate length, 4-nm thick ultrathin SOI n-MOSFET shows the S-slope of only 75 mV and the ΔV_th of only 0.07 V as compared to the value in the case of the long gate-length (135 nm) device. Based on these experimental results, the remarkable advantage of an ultrathin SOI channel in suppressing the short-channel effects is confirmed for future MOS devices

Keywords

MOSFET; semiconductor device measurement; semiconductor epitaxial layers; silicon-on-insulator; 4 to 18 nm; 40 to 135 nm; Si; channel SOI thickness; gate length; short-channel effects; subthreshold slope; threshold voltage roll-off; ultrathin SOI n-MOSFETs; Circuit simulation; Conductivity; Laboratories; MOS devices; MOSFET circuits; Proposals; Silicon on insulator technology; Substrates; Threshold voltage; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.822280

Filename

822280