DocumentCode
1299586
Title
A p-channel MOS synapse transistor with self-convergent memory writes
Author
Diorio, Chris
Author_Institution
Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
Volume
47
Issue
2
fYear
2000
fDate
2/1/2000 12:00:00 AM
Firstpage
464
Lastpage
472
Abstract
We have developed a p-channel floating-gate-MOS synapse transistor for silicon-learning applications. The synapse stores a nonvolatile analog weight by means of charge on its floating gate, modifies this weight bidirectionally using electron tunneling and hot-electron injection, and allows simultaneous memory reading and writing. The synapse also learns locally-its weight updates depend only on the applied terminal voltages and on the stored weight. We fabricated an array of synapses that computed both the array output, and the weight updates, in parallel. We also demonstrated a self-convergent write procedure that permitted accurate initialization of the synapse weights. Our pFET synapse is small, and is operated at subthreshold current levels; it will permit the development of dense, low-power, silicon learning systems
Keywords
CMOS memory circuits; MOSFET; analogue processing circuits; analogue storage; hot carriers; tunnelling; accurate initialization; applied terminal voltages; electron tunneling; floating gate charge; floating-gate-MOS transistor; hot-electron injection; nonvolatile analog weight; p-channel MOS synapse transistor; pFET synapse; self-convergent memory writes; self-convergent write procedure; silicon-learning applications; simultaneous memory reading/writing; stored weight; subthreshold current levels; synapse array; synapse weights; weight updates; Concurrent computing; MOSFETs; Nonvolatile memory; Read-write memory; Secondary generated hot electron injection; Silicon; Subthreshold current; Tunneling; Voltage; Writing;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.822295
Filename
822295
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