A Phase-Locked Loop With Background Leakage Current Compensation

Author

Chang, Jung-Yu ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

57

Issue

9

fYear

2010

Firstpage

666

Lastpage

670

Abstract

A background compensation method is presented to compensate the leakage current of MOS capacitors for phase-locked loops (PLLs) in nanoscale CMOS technology. A leakage detection circuit is used to adjust a voltage-controlled current source to compensate the leakage current. This PLL has been fabricated in 65-nm CMOS technology. With the background leakage current compensation, the measured peak-to-peak and rms jitters of this PLL at 1 GHz are 36 and 4.54 ps, respectively. Its power consumption is 8.4 mW for a 1.2-V supply voltage.

Keywords

CMOS integrated circuits; MOS capacitors; leakage currents; phase locked loops; CMOS technology; MOS capacitors; background leakage current compensation; frequency 1 GHz; leakage detection circuit; phase-locked loop; power 8.4 mW; size 65 nm; voltage 1.2 V; voltage-controlled current source; Capacitors; Converters; Current measurement; Jitter; Leakage current; Phase locked loops; Voltage-controlled oscillators; Background; leakage current compensation; leakage detection; phase-locked loop (PLL);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2010.2056013

Filename

5551183