An approach for detecting multiple faulty FPGA logic blocks

Author

Huang, Wei Kang ; Meyer, Fred J. ; Lombardi, Fabrizio

Author_Institution

Syst. State Key Lab., Fudan Univ., Shanghai, China

Volume

49

Issue

1

fYear

2000

fDate

1/1/2000 12:00:00 AM

Firstpage

48

Lastpage

54

Abstract

An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC4000, and XC5200 families were studied. The proposed AND/OR approach was found to reduce the number of FPGA reprogrammings needed for testing by up to a factor of seven versus direct methods of multiple faulty block detection

Keywords

fault tolerant computing; field programmable gate arrays; logic design; programmable logic devices; AND tree; OR tree-based testing; XC4000; XC5200; Xilinx XC3000; configuration memories; constant testability; multiple faulty FPGA logic blocks detection; multiple faulty block detection; Electrical fault detection; Fault detection; Fault tolerance; Field programmable gate arrays; Logic testing; Programmable logic arrays; Programmable logic devices; Routing; Test pattern generators; Wires;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.822563

Filename

822563