DocumentCode
1300159
Title
SET Emulation Considering Electrical Masking Effects
Author
Entrena, Luis ; Valderas, Mario García ; Cardenal, Raúl Fernández ; García, Marta Portela ; Ongil, Celia López
Author_Institution
Electron. Technol. Dept., Univ. Carlos III of Madrid, Leganes, Spain
Volume
56
Issue
4
fYear
2009
Firstpage
2021
Lastpage
2025
Abstract
A new approach is proposed for evaluating circuit robustness against Single Event Transients (SETs) through FPGA emulation. A voltage-time quantization model allows capturing circuit delays in the FPGA, including electrical masking effects. Experimental results demonstrate this approach improves SET fault injection rate by three orders of magnitude with respect to logic simulation and provides an accuracy close to analog simulation.
Keywords
delays; field programmable gate arrays; masks; FPGA emulation; SET fault injection rate; analog simulation; circuit delays; circuit robustness; logic simulation; single event transient emulation; voltage-time quantization model; Circuit faults; Circuit simulation; Delay effects; Emulation; Error analysis; Field programmable gate arrays; Logic; Quantization; Single event upset; Transient analysis; Electrical masking; FPGA emulation; fault injection; single event transient (SET);
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2009.2013346
Filename
5204761
Link To Document