• DocumentCode
    1300363
  • Title

    Optimized test circuits for SER characterization of a manufacturing process

  • Author

    Hazucha, Peter ; Svensson, Christer

  • Author_Institution
    Dept. of Electron. Devices, Linkoping Univ., Sweden
  • Volume
    35
  • Issue
    2
  • fYear
    2000
  • Firstpage
    142
  • Lastpage
    148
  • Abstract
    Novel test circuits for the accurate determination of soft error rate (SER) dependency on critical charges Q/sub CRIT/ have been developed. The minimum charge necessary for flipping the state of a sensor cell, denoted by Q/sub CRIT/, is measured with 1%-2% accuracy before exposing the circuits to radiation. During the accelerated testing, circuits biased with multiple different supply voltages V/sub CC/ are simultaneously placed into a beam and any bit flips are logged. From the measured SER dependency on V/sub CC/ and previously measured Q/sub CRIT/ dependency on V/sub CC/, the dependency of SER on Q/sub CRIT/ can be deduced by correlating V/sub CC/´s for the two measurements. Furthermore, the sensor cell utilizes a single dynamic node which can be programmed to detect strikes on either N- or P-type diffusions, but not both at the same time. The measured dependency SER(Q/sub CRIT/), normalized by the diffusion area, can be used for predicting SER of any other circuit fabricated in the same process and aid designers in optimization for reduced SER. Predictions of a theoretical SER model, if one is available, can be compared directly with the measurements. Since the true Q/sub CRIT/ of the test circuits is known accurately, any discrepancy larger than given by the measurement uncertainty of SER(Q/sub CRIT/) would be clearly due to limitations of the SER model. We implemented the test circuits in a 0.6-/spl mu/m bulk CMOS process and verified accuracy of Q/sub CRIT/(V/sub CC/) calibration method.
  • Keywords
    CMOS integrated circuits; digital simulation; errors; integrated circuit manufacture; integrated circuit reliability; integrated circuit testing; life testing; production testing; radiation effects; SER characterization; SER dependency; SEU; accelerated testing; biased; bit flips; bulk CMOS process; calibration method; critical charges; diffusion area; manufacturing process; multiple different supply voltages; n-type diffusions; optimization; optimized test circuits; p-type diffusions; radiation exposure; sensor cell; single dynamic node; single event upset; soft error rate; strike detection; Charge measurement; Circuit testing; Current measurement; Error analysis; Life estimation; Manufacturing; Particle beams; Q measurement; Sensor phenomena and characterization; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.823440
  • Filename
    823440