On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

A novel VLSI design for a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous study is replaced by a time-domain algorithm through a detailed comparison of their VLSI implementations. An architecture that implements the time-domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, an implementation of Euclid´s algorithm maintains the throughput rate with less circuitry. Some improvements result in both enhanced capability and significant reduction in silicon area, making it possible to build the decoder on a single chip