A fully integrated 0.5-5.5 GHz CMOS distributed amplifier

Author

Ballweber, Brian M. ; Gupta, Ravi ; Allstot, David J.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

35

Issue

2

fYear

2000

Firstpage

231

Lastpage

239

Abstract

A fully integrated 0.5-5.5-GHz CMOS-distributed amplifier is presented. The amplifier is a four stage design fabricated in a standard 0.6-/spl mu/m three-layer metal digital-CMOS process. The amplifier has a unity-gain cutoff frequency of 5.5 GHz, and a gain of 6.5 dB, with a gain flatness of /spl plusmn/1.2 dB over the 0.5-4 GHz band. Input and output are matched to 50 /spl Omega/, with worst-case return losses on the input and output of -7 and -10 dB, respectively. Power dissipation is 83.4 mW from a 3.0 V supply, input-referred 1-dB compression point varies from +6 dBm at 1 GHz to 8.8 dBm at 5 GHz. From a circuit standpoint, the fully integrated nature of the amplifier on the given substrate results in a heavily parasitic-laden design. Discussion emphasis is therefore placed on the practical design, modeling, and CAD optimization techniques used in the design process.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; circuit CAD; circuit optimisation; distributed amplifiers; integrated circuit design; integrated circuit modelling; simulated annealing; wideband amplifiers; 0.5 to 5.5 GHz; 0.6 micron; 3 V; 5 GHz; 6.5 dB; 83.4 mW; CAD optimization techniques; CMOS distributed amplifier; four stage design; modeling; parasitic-laden design; three-layer metal CMOS process; CMOS technology; Capacitance; Cutoff frequency; Design optimization; Distributed amplifiers; Gain; Inductors; Process design; Radiofrequency amplifiers; Substrates;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.823448

Filename

823448