A pipeline A/D converter architecture with low DNL

Author

Opris, Ion E. ; Wong, Bill C. ; Chin, Sing W.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

Volume

35

Issue

2

fYear

2000

Firstpage

281

Lastpage

285

Abstract

A pipeline analog-to-digital converter architecture can reduce the differential nonlinearity (DNL) with a swapping technique without involving special calibration techniques. An implementation of the overrange stages in the analog pipeline suitable for high-speed applications is proposed. A 14-bit 5-MSample/s converter has been fabricated in a double-poly 0.5-/spl mu/m CMOS process. The 3.3/spl times/3.3 mm/sup 2/ chip dissipates 320 mW from a single 5 V supply and achieves a signal-to-noise ratio of 79 dB, a dynamic range of 82 dB, and a DNL below 0.4 LSB.

Keywords

CMOS integrated circuits; analogue-digital conversion; pipeline processing; switched capacitor networks; 0.5 micron; 14 bit; 320 mW; 5 V; 79 dB; SNR; analog-to-digital converter; differential nonlinearity reduction; double-poly CMOS process; dynamic range; high-speed applications; overrange stages; pipeline A/D converter; pipeline ADC architecture; signal-to-noise ratio; swapping technique; Analog-digital conversion; CMOS process; Calibration; Capacitors; Feedback; Linearity; Operational amplifiers; Pipelines; Signal to noise ratio; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.823454

Filename

823454