Title :
A pseudologarithmic rectifier using unbalanced bias MFMOS differential pairs
Author :
Mehrvarz, Hamid Reza ; Kwok, Chee Yee
Author_Institution :
Sch. of Electr. Eng., New South Wales Univ., Kensington, NSW, Australia
fDate :
1/1/1998 12:00:00 AM
Abstract :
A pseudologarithmic rectifier using multi-input floating-gate MOS (MFMOS) transistors is presented in this paper. The rectifiers consist of unbalanced bias matched MFMOS transistor differential pairs. The transfer characteristics of each subrectifier are determined by an appropriate choice of transistor aspect ratio and capacitive input coupling ratio such that in the summation of the output currents from each rectifier stage, the overall transfer characteristics closely approximates that of a true logarithmic behavior. It is operable at low supply voltage (±0.9 V) and has low temperature dependence. Measured dynamic range of 27 dB and 16.5 dB, with a corresponding logarithmic error of ±0.7 dB and ±0.35 dB, has been obtained for three-stage and two-stage pseudologarithmic rectifiers, respectively, at room temperature. The measured logarithmic error for the three-stage pseudologarithmic rectifier at 125°C is ±1.05 dB which is an increase of ±0.35 dB over a 100°C range
Keywords :
MOSFET circuits; solid-state rectifiers; 0.9 V; 125 C; aspect ratio; capacitive input coupling ratio; dynamic range; logarithmic error; low voltage circuit; multi-input floating-gate MOS transistor; pseudologarithmic rectifier; temperature dependence; three-stage rectifier; transfer characteristics; two-stage rectifier; unbalanced bias matched MFMOS differential pair; CMOS technology; Capacitance; Differential amplifiers; Dynamic range; Low voltage; MOSFETs; Rectifiers; Temperature dependence; Temperature distribution; Temperature measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
