Title :
Optimizing MOS transistor mismatch
Author :
Lovett, Simon J. ; Welten, Marco ; Mathewson, Alan ; Mason, Barry
Author_Institution :
Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland
fDate :
1/1/1998 12:00:00 AM
Abstract :
An investigation of MOS transistor mismatch is undertaken and a methodology is developed for optimizing mismatch without increasing layout area. Dramatic improvements of up to 300% in matching can be realized by selecting the optimum W/L ratio without changing the overall WL area product. The theoretical basis for the obtainable improvements is fully described and an expression is derived and verified by experiment to predict the W/L ratio which gives optimum matching
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit layout; MOS transistor mismatch; MOSFET mismatch optimisation; optimum W/L ratio; Analytical models; Geometry; Integrated circuit modeling; MOS devices; MOSFETs; Microelectronics; Mixed analog digital integrated circuits; Optimization methods; Testing; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
