DocumentCode
1300867
Title
A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
Author
Seng, Yeo Kiat ; Rofail, Samir S.
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
Volume
33
Issue
1
fYear
1998
fDate
1/1/1998 12:00:00 AM
Firstpage
164
Lastpage
168
Abstract
New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits´ performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-μm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates
Keywords
BiCMOS digital integrated circuits; BiCMOS logic circuits; adders; logic design; logic gates; 0.8 micron; LV BiCMOS logic circuits; XOR gate; adder; charge-trapping-based technique; low-voltage logic circuit design; submicron technologies; Adders; BiCMOS integrated circuits; CMOS logic circuits; Circuit simulation; Degradation; Logic circuits; Logic gates; Propagation delay; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.654950
Filename
654950
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