A 1.0-GHz 0.6-μm 8-bit carry lookahead adder using PLA-styled all-N-transistor logic

Author

Wang, Chua-Chin ; Huang, Chenn-Jung ; Tsai, Kun-Chu

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

47

Issue

2

fYear

2000

fDate

2/1/2000 12:00:00 AM

Firstpage

133

Lastpage

135

Abstract

This article presents a high-speed 8-bit carry-lookahead adder (CLA) using two-phase clocking dynamic CMOS logic with modified noninverting all-N-transistor (ANT) blocks which are arranged in a programmable logic array design style. Detailed simulation reveals appropriate L/W guidelines for the ANT block design. The area (transistor count) tradeoff is also analyzed. The operating clock frequency is 1.0 GHz, while the output of the addition of two 8-bit binary numbers is completed in two cycles. Simulation results confirm that the proposed design methodology is appropriate for the long adders, e.g., 64-bit adders, while the correct output is available after four cycles if the 64-bit adder is composed of nine hierarchical 8-bit CLA´s

Keywords

CMOS logic circuits; adders; high-speed integrated circuits; programmable logic arrays; 0.6 micron; 1.0 GHz; 8 bit; circuit simulation; design methodology; dynamic CMOS logic; high-speed carry-lookahead adder; noninverting all-N-transistor logic block; programmable logic array; two-phase clocking; Assembly; CMOS logic circuits; Clocks; Design methodology; Frequency; Guidelines; Logic design; Programmable logic arrays; Robustness; Threshold voltage;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.823541

Filename

823541