DocumentCode
1301655
Title
FPGA adders: performance evaluation and optimal design
Author
Xing, Shanzhen ; Yu, William W H
Author_Institution
Hong Kong Univ., Hong Kong
Volume
15
Issue
1
fYear
1998
Firstpage
24
Lastpage
29
Abstract
Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders
Keywords
adders; circuit optimisation; field programmable gate arrays; logic design; minimisation of switching nets; performance evaluation; timing; ASIC technology; FPGA adders; Xilinx 4000; carry-select adders; carry-skip; fixed-point adders; optimal design; performance evaluation; timing models; Adders; Application specific integrated circuits; Cost function; Delay; Field programmable gate arrays; Logic arrays; Logic devices; Testing; Timing; Very large scale integration;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.655179
Filename
655179
Link To Document