Title :
A High-Speed and EDP-Efficient Range-Matching Scheme for Packet Classification
Author :
Zhang, Jian-Wei ; Yu, Ming-yan ; Liu, Bin-Da ; Huang, Xiao-Feng
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., Harbin, China
Abstract :
A range-matching scheme for packet classification (PC) that greatly improves search speed is presented. It effectively reduces the energy delay product (EDP) and increases the storage efficiency by up to 2.5 times over conventional ternary content addressable memories (TCAMs) under typical PC rule sets. Simulation results show that the proposed 16-bit range-matching word (RMW) achieves a 1.53-ns search time, which is a 70.5% delay reduction over that by Kim et al. The EDP index is also reduced to 45% that by Kim et al. A 64 word times 144 bit prototype chip whose word circuit comprises two 16-bit RMWs, a 104-bit TCAM word, and an 8-bit filter implemented using a 3.3-V 0.35-mum complementary metal-oxide-semiconductor (CMOS) process achieves a 2.5-ns range-matching delay time with an energy index of 28.7 fJ/bit/search for the total word circuit.
Keywords :
CMOS memory circuits; computer networks; content-addressable storage; CMOS process; complementary metal-oxide-semiconductor process; energy delay product; packet classification; range matching; ternary content addressable memories; word length 104 bit; word length 16 bit; Energy delay product (EDP); high speed; packet classification (PC); range matching;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2009.2027946
