Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

Author

Hamill, Robert ; McCanny, John V. ; Walke, Richard L.

Author_Institution

Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK

Volume

48

Issue

2

fYear

2000

fDate

2/1/2000 12:00:00 AM

Firstpage

592

Lastpage

598

Abstract

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an online CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-μ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamforming can be readily accommodated on a single chip

Keywords

CMOS digital integrated circuits; VLSI; convergence of numerical methods; digital arithmetic; digital signal processing chips; parallel algorithms; radar signal processing; systolic arrays; 0.35 mum; CMOS standard cell process; QR decomposition; QR-array processors; VLSI architecture; VLSI design; constant scale factor; convergence bounds; most significant digit first; online CORDIC algorithm; radar beamforming; single chip architecture; systolic array processor cells; wordlength independent latency; Arithmetic; Array signal processing; CMOS process; Convergence; Delay; Laboratories; Process design; Signal processing algorithms; Systolic arrays; Very large scale integration;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.823992

Filename

823992