DocumentCode
1302399
Title
Efficient Power Network Analysis Considering Multidomain Clock Gating
Author
Zhang, Wanping ; Yu, Wenjian ; Hu, Xiang ; Zhang, Ling ; Shi, Rui ; Peng, He ; Zhu, Zhi ; Chua-Eoan, Lew ; Murgai, Rajeev ; Shibuya, Toshiyuki ; Ito, Noriyuki ; Cheng, Chung-Kuan
Author_Institution
Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, CA, USA
Volume
28
Issue
9
fYear
2009
Firstpage
1348
Lastpage
1358
Abstract
In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial fraction expression, which can be easily converted to a time-domain waveform. Then, an algorithm is proposed to find the worst-case voltage variation and corresponding clock gating patterns, through superimposing the voltage responses caused by all domains working separately. The major computation of the whole framework is solving the frequency-domain equation system, whose complexity is about O(NalphaD log f max), where alpha is between one and two if using an iterative solver from the PETSc library. N is the node number, f max is the upper bound of frequency, and D is the number of clock domains. Numerical results show that the proposed simulation method is up to several hundred times faster than commercial fast simulators, like HSPICE and MSPICE. In addition, the proposed method is able to analyze large-scale power networks that the commercial tools are not able to afford.
Keywords
SPICE; clocks; distribution networks; frequency-domain analysis; iterative methods; logic circuits; time-domain analysis; transmission networks; HSPICE; MSPICE; PETSc library; frequency-domain-based simulation method; iterative solver; multidomain clock gating; node number; numerical simulation method; partial fraction expression; power network analysis; time-domain voltage response; vector fitting technique; worst-case voltage variation; Frequency-domain analysis; multidomain clock gating; power network; vector fitting (VF); worst-case voltage variation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2009.2024711
Filename
5208485
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