A hardware efficient control of memory addressing for high-performance FFT processors

Author

Ma, Yutai ; Wanhammar, Lars

Author_Institution

Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden

Volume

48

Issue

3

fYear

2000

fDate

3/1/2000 12:00:00 AM

Firstpage

917

Lastpage

921

Abstract

The conventional memory organization of fast Fourier transform (FFT) processors is based on Cohen´s (1976) scheme. Compared with this scheme, our scheme reduces the hardware complexity of address generation by about 50% while improving the memory access speed. Much power consumption in memory is saved since only half of the memory is activated during memory access, and the number of coefficient access is reduced to a minimum by using a new ordering of FFT butterflies. Therefore, the new scheme is a superior solution to constructing high-performance FFT processors

Keywords

computational complexity; digital signal processing chips; fast Fourier transforms; hypercube networks; read-only storage; storage allocation; Cohen´s scheme; FFT butterflies; ROM; address generation; coefficient access reduction; fast Fourier transform; hardware complexity reduction; hardware efficient control; high-performance FFT processors; memory access speed; memory addressing; memory organization; memory power consumption; Energy consumption; Fast Fourier transforms; Focusing; Hardware; Image processing; Memory architecture; Process control; Radar signal processing; Read only memory; Signal processing algorithms;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.824693

Filename

824693