Title :
Lessons and Experiences with High-Level Synthesis
Author :
Sarkar, Soujanna ; Dabral, Shashank ; Tiwari, Praveen K. ; Mitra, Raj S.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
Electronic system level (ESL) design has attracted considerable attention in the past few years, and high level synthesis is a significant component of ESL design. Despite advances in HLS algorithms, the RTL remains the dominant specification and synthesis level. This article is a designer´s perspective on the benefits and challenges of using commercially available HLS tools. They discuss their impact on four criteria: design goals, verification closure, eco handling, and productivity gains.
Keywords :
high level synthesis; ESL; HLS design goal; HLS eco handling; HLS productivity gains; HLS verification closure; electronic system level; high level synthesis; Application specific integrated circuits; Delay; Design optimization; High level synthesis; Instruments; Power system modeling; Productivity; Prototypes; Silicon; Throughput; ASIC; ESL design; design and test; high-level synthesis;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2009.84
